Self aligned notch for InP planar transferred electron oscillator

ABSTRACT

A method of fabricating a notched indium phosphide planar transferred electron oscillator device which automatically aligns the high-resistivity notch position immediately adjacent to the cathode contact by slant evaporation of a metal coating over the edge of a masking layer followed by ion implantation.

BACKGROUND OF THE INVENTION

The present invention is directed to transferred electron oscillators(TEOs), and more particularly to methods for fabricating InP TEOs.

Indium phosphide has excellent material properties for the operation ofTEO devices in the millimeter-wave region of the radio spectrum. As aresult of these material properties, high efficiency oscillators andlow-noise broadband amplifiers have been developed. The devices used forthe oscillator and amplifier development have been fabricated on n⁺substrates, and accordingly, integration within a monolithic format isnot easily achieved. For further application in millimeter-wavemonolithic circuits, this work has focused on the development of aplanar transferredelectron device formed on a semi-insulating substrate.

Planar InP TEOs have been constructed whose design includes a localizedhigh resistivity region near the cathode contact. The high resistivityregion, referred to as a notch, partially extends into the active layerand is formed by selective boron implanatation damage. This designcreates a localized high electric field region, which produces alaterally uniform well-defined space-charge nucleation site. The notcheddevices demonstrate significantly superior microwave performancecompared to devices without a notch. At x-band, notched TEO devicesoperate with direct current (DC) to radio frequency (RF) conversionefficiencies of up to 4.5 percent, while the TEO devices without a notchoperate with an efficiency of less than 1 percent.

However for highest efficiency, the region of selective ion implantationmust be aligned between the TEO device cathode and anode contacts, asclose as possible to the cathode contact. As the device dimensions aredecreased to meet the need of higher frequency operation, a differentmethod of fabrication must be employed to accurately position the notchnext to the cathode contact.

OBJECTS OF THE INVENTION

Accordingly, one object of the invention is to fabricate ahigh-efficiency planar InP TEO device.

Another object of the invention is to fabricate a high-efficiency planarInP TEO device for operation at extremely high frequencies.

Yet another object of the invention is to fabricate a high-efficiencyplanar InP TEO whcih includes an aligned high resistivity notch regionin the device substrate between the device cathode and anode contacts.

Still another object of the invention is to fabricate a high efficiencyplanar InP TEO device which includes the high resistivity notch regionin the device substrate aligned immediately adjacent to the cathodecontact.

A further object of the invention is to fabricate a high efficiencyplanar InP TEO device which includes automatically aligning the highresistivity notch region in the device substate adjacent to the cathodecontact.

SUMMARY OF THE INVENTION

These and other objects of the invention are achieved by a method offabrication which includes applying a masking layer with voids in it todefine cathode and anode region metallization patterns, slantevaporating a metallic film onto the masking layer to form an uncoatedregion adjacent to the cathode region, and ion implanting the uncoatedarea to form a high resistivity notch region in the substrateimmediately adjacent to the cathode region. Removal of the masking layerwith its metallic film coating followed by alloying then forms a planarInP TEO device structure with an automatically aligned high resistivitynotch region.

Other objects, features and advantages of the invention will be apparentto those skilled in the art in the description of the preferredembodiment of the invention as described below and also recited in theappended claims.

DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a self-aligned notch InP TEO device as produced by thefabrication process according to the invention.

FIG. 2 shows the doped semiconductor substrate selected for thefabrication process according to the invention.

FIG. 3 shows the slant evaporation phase of the fabrication processaccording to the invention.

FIG. 4 shows the oxygen implanatation phase of the fabrication processaccording to the invention.

FIG. 5 shows the completed self-aligned TEO structure after the alloyingphase of the fabrication process according to the invention.

DESCRIPTION OF THE PREFERRED EMBODIMENT

Referring to the drawings, wherein like reference characters designatelike or corresponding parts throughout the views, FIG. 1 shows across-sectional side view of the desired device structure for theself-aligned InP TEO. An indium phosphide substrate 10 has an n-dopedepitaxial surface layer 12. The surface layer 12 includes an n⁺ -dopedanode region 14 which partially penetrates the surface layer 12. Theanode region 14 has an ohmic anode contact 16 on its surface. An area ofsaid surface layer 12 has an ohmic cathode contact 18 on its surface.Between the cathode contact 18 and the anode contact 16, ahigh-resistivity impurity-containing notch region 20 partiallypenetrates the surface layer 12 immediately adjacent to the cathodecontact 18.

The fabrication process of the invention is illustrated in FIGS. 2through 5. As shown in FIG. 2, a semi-insulating InP substate 22 isselected having an epitaxially grown n-type InP surface layer 24 with atleast one n⁺ -doped anode region 26 imbedded in the surface layer 24. Byway of example, a suitable substrate 22 may have an epitaxial surfacelayer 24 in the range of 0.8 to 1.5 μm in thickness, but preferably inthe range of 0.9 μm in thickness, with a carrier concentration in therange of 1 to 10×10¹⁶ cm⁻³, but preferably in the range of 6×10¹⁶ cm⁻³,and the n⁺ -doped anode region 26 may be formed in the surface layer 24by selective ion implantation, as will be recognized by those skilled inthe art.

As shown in FIG. 3, a masking layer 28, which may be, by way of example,a photoresist mask in the range of 1 μm in thickness, is applied overthe surface of the surface layer 24. The masking layer 28 includes twovoids through it, one void over the anode region 26, and the other voidclosely spaced to the anode region to define a cathode region 30. Ametallization layer 32 is then evaporated onto the masking layer 28 atan angle from perpendicular to the masking layer 28, having a slant in adirection from the anode region 26 toward the cathode region 30. By wayof example, the metallization layer 32 may comprise a laminate of goldover gold germanium layers each in the range of 1000 Å in thickness,evaporated onto the masking layer 28 at an angle in the range of 10 to45 degrees, but preferably in the range of 22 degrees. By evaporatingthe metallization layer 32 at an angle, the metallization layer 32acquires a narrow void region 34 between the cathode region 30 andmasking layer 28 due to the shadow effect of the edge of the maskinglayer 28.

As shown in FIG. 4, the surface of the metallization layer 32 is thensubjected to ion implantation. Ions only penetrate into the substratesurface layer 24 through the metallic layer void region 34, creating ahigh resistivity notch region 36 penetrating the surface layer 24. Byway of example, oxygen atoms may be implanted to create the highresistivity notch region 36.

As shown in FIG. 5, the masking layer 28 is then chemically removed, andthe portion of the metallization layer in contact with it is strippedoff. The substrate is then alloyed to change the remaining portion ofthe metallization layer 32 covering the cathode region 30 into an ohmiccathode contact 38, and the portion covering the anode region 26 to anohmic contact 40. By way of example, alloying at a temperature of about400° C. for a period of 30 seconds is sufficient, as will be apparent tothose skilled in the art.

It will be understood that various changes in the details, materials andarrangement of steps and components which have been herein described andillustrated in order to explain the nature of the invention may be madeby those skilled in the art.

What is claimed and desired to be secured by Letters Patent of theUnited States is:
 1. A method of fabricating an indium phosphidetransferred-electron oscillator device comprising the steps of:selectinga semi-insulating indium phosphide substrate with an epitaxial n-typesurface layer and an n⁺ -doped anode region in said surface layer;applying a masking layer over said surface layer including a first voidover said anode region and a second void over an adjacent cathoderegion; evaporating a metallization layer at an angle from perpendicularto said masking layer, having a slant in a direction from said anoderegion to said cathode region, to create a narrow void in saidmetallization layer adjacent to said cathode region due to shadow effectof said masking layer; implanting impurity ions into said surface layerthrough said metallization layer void to create a narrowhigh-resistivity region adjacent to said cathode region; removing saidmasking layer with the portion of said metallization layer whichcontacts it, to create a cathode region metallization layer over saidcathode region and an anode region metallization layer over said anoderegion; and alloying said substrate to convert said cathodemetallization layer to an ohmic cathode contact and said anodemetallization layer to an anode ohmic contact.
 2. The method offabricating an indium phosphide transfered-electron oscillator device asrecited in claim 1, wherein the step of slant evaporating ametallization layer further comprises evaporating said metallizationlayer at said slant angle in the range of 10 to 45 degrees fromperpendicular to said masking layer.
 3. The method of fabricating anindium phosphide transferred-electron oscillator device as recited inclaim 2, wherein the step of applying a masking layer over said surfacelayer further comprises applying said masking layer with a thickness inthe range of 1 μm.
 4. The method of fabricating an indium phosphidetransferred-electron oscillator device as recited in claim 3, whereinthe step of selecting a semi-insulating indium phosphide substratefurther comprises selecting said substrate having said epitaxial n-typesurface layer with a thickness in the range of 0.8 to 1.5 μm.
 5. Themethod of fabricating an indium phosphide transferred-electronoscillator device as recited in claim 4, wherein the step of selecting asemi-insulating indium phosphide substrate further comprises selectingsaid substrate having said epitaxial n-type surface layer with a carrierconcentration in the range of 1 to 10×10¹⁶ cm⁻³.
 6. The method offabricating an indium phosphide transferred-electron oscillator deviceas recited in claim 5, wherein the step of applying a masking layerfurther comprises applying said masking layer selected from the group ofphotoresist materials.
 7. The method of fabricating an indium phosphidetransferred-electron oscillator device as recited in claim 6, whereinthe step of slant evaporating a metallization layer further comprisesslant evaporating a metallization layer of gold over gold germaniumlaminate layers.
 8. The method of fabricating an indium phosphidetransferred-electron oscillator device as recited in claim 7, whereinthe step of removing said masking layer further comprises chemicallyremoving said masking layer.
 9. The method of fabricating an indiumphosphide transferred-electron oscillator device as recited in claim 8,wherein the step of slant evaporating a metallization layer furthercomprises evaporating said gold over gold germanium laminate layer witha gold lamination thickness and a gold germanium lamination thicknesseach in the range of 1000 Å.
 10. A method of fabricating an indiumphosphide transferred-electron oscillator device comprising the stepsof:selecting a semi-insulating indium phosphide substrate with anepitaxial surface layer having a thickness in the range of 0.9 μm and acarrier concentration in the range of 6×10¹⁶ cm⁻³, and an n⁺ -dopedanode region in said surface layer; applying a masking layer over saidsurface layer having a thickness in the range of 1 μm including a firstvoid over said anode region and a second void over an adjacent cathoderegion; evaporating a metallization layer comprising a laminate of goldin the range of 1000 Å in thickness over gold germanium in the range of1000 Åin thickness, at an angle from perpendicular to said masking layerin the range of 22 degrees, having a slant in a direction from saidanode region to said cathode region, to create a narrow void in saidmetallization layer adjacent to said cathode region due to shadow effectof said masking layer; implanting impurity ions into said surface layerthrough said metallization layer void to create a narrowhigh-resistivity region adjacent to said cathode regions; chemicallyremoving said masking layer with the portion of said metallization layerwhich contacts it, to create a cathode region metallization layer oversaid cathode region and an anode region metallization layer over saidanode region; and alloying said substrate at a temperature in the rangeof 400° C. for a time period in the range of 30 seconds to convert saidcathode metallization layer to an ohmic cathode contact and said anodemetallization layer to an anode ohmic contact.